A cache memory (Cache) is a storage unit capable of temporarily storing data transparently, and the access of a processing unit to the cache memory is faster than the access to a lower level storage unit. Operations on the cache memory include operations such as Write Allocate (Write Allocate), Not Write Allocate (Not Write Allocate), Read Allocate (Read Allocate), Not Read Allocate (Not Read Allocate) and Read Invalidate (Read Invalidate).
In writing data into the Cache, if a corresponding write address does not exist in the Cache, a write miss occurs; at this time, a corresponding memory block is loaded in the Cache, and then a cache block is updated, which is the Write Allocate operation.
In writing data into the Cache, if a corresponding write address does not exist in the Cache, a write miss occurs; at this time, data is directly written into a lower level memory and no address is allocated in the Cache, which is the Not Write Allocate operation.
In reading data from the Cache, if a corresponding read address does not exist in the Cache, a read miss occurs; at this time, a corresponding memory block of the lower level memory is loaded in the Cache, and then data is fed back to the processing unit, which is the Read Allocate operation.
In reading data from the Cache, if a corresponding read address does not exist in the Cache, a read miss occurs; data is directly read from the lower level memory and returned to the processing unit, and no address is allocated in the Cache, which is the Not Read Allocate operation.
In the process of reading data, if the data being read is hit in the Cache, after the data is sent to a read operation initiation module, a corresponding CacheLine is set to an invalid state, so that when a new operation is accessed, the CacheLine may be allocated new data and no Cache conflict occurs.
The existing service processing has a fixed feature that use frequencies of different data, such as a packet header, a packet payload and a service processing intermediate variable, are quite different, and the use frequencies of the packet header and the service processing intermediate variable are obviously higher than the use frequency of the packet payload. When processing data, the processing unit, based on this feature, treats the data differently according to a specific rule to place frequently used data in the Cache near the processing unit, so as to increase processing speed and improve system processing performance. In addition, power consumption for accessing the data in the Cache is higher than the power consumption for accessing the data in a lower storage level. Therefore, controlling data access on a storage level closer to the processing unit as much as possible is helpful in both improving the performance and reducing the power consumption.
During the implementation of the present invention, the inventor discovers that the prior art has at least the following problems:
The capacity of the Cache is limited, incapable of storing all the data during processing, so that the data inevitably needs to be stored in the lower level memory, data replacement and interaction constantly occur between the Cache and the lower level memory, and data being processed and frequently used may be replaced into the lower level memory of the Cache by input high traffic data. As a result, the hit rate of the Cache is lowered, the power consumption of a device is increased, and the processing bandwidth of a processing node is affected, so that the system performance is greatly deteriorated with the increase of the processing bandwidth and processing complexity.